Volume 15, No 2, 2018
Enhancing Embedded Memory Testability: Microcode BIST Optimization For Superior Fault Detection
Meer Tabres Ali and Dr. A A Ansari
Abstract
The abstract focuses on the escalating challenges of faults in embedded memory as chip area and density advance. It introduces an architectural solution that incorporates new March algorithms—specifically the March BLC algorithm—for enhanced fault detection in memory systems. The project develops a design-for-test (DFT) strategy using VHDL for microcode-based built-in self-test (BIST) for embedded memory cards. It models the architecture at the register transfer level and simulates two distinct testing algorithms. The performance is evaluated based on the logic gate count, denoting the circuit's area, and the time efficiency of the memory testing process.
Pages: 260-269
Keywords: Embedded Memory, Testability, Microcode BIST (Built-In Self-Test), Fault Detection, March Algorithms, March BLC Algorithm, Design for Test (DFT), VHDL (Very High-Speed Integrated Circuit Hardware Description Language), Microcode Architecture, Register Tra