Volume 18, No. 6, 2021
Charge Sharing Tolerant Domino With Contention Current Partitioning For Wide Fan-In OR Logic Gates
Sourabh Yadav , Rahul Gupta , Manjeet Singh Sonwani , Chetna Sinha , Sanjay Kumar Dewangan
Abstract
This paper presents a charge-sharing tolerant domino circuit technique. The technique is composed of dual strategy to cope up with the charge sharing in domino circuits due to transistor loading at wide fan in and due to the current contention at keeper stage respectively. The proposed Charge Sharing Tolerant Domino or CSTD works primarily to engage in isolating the drain circuit from the short circuit current, thereby avoiding the leakage-related losses and charge sharing of the domino circuit. Secondly, CSTD uses a modified keeper circuit to reduce the contention current at keeper stage. The proposed circuit has been studied and performance optimized. CSTD is compared with the standard footer and footless domino, and other latest domino circuit techniques. CSTD results in 51.2% reduced power consumption as compared to SFD and 18.9% as compared to the latest LPSD circuit technique, at 64 bit fan-in. The noise metric as determined by Average Noise Immunity has been substantially improved by 189% as compared to SFD and 37% as compared to LPSD. Simulation environment was kept at 90nm NMOS and PMOS models, at 500MHz.
Pages: 7127-7144
Keywords: The dynamic logic circuit is a next-generation logic style that uses the circuit’s inherent parasitic capacitance to provide the output voltage without the necessity of keeping a low impedance path from output to voltage supply or ground always [1-6].